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19-3361; Rev 2; 3/05
Dual, Quad, and Hex High-Speed Differential ESD-Protection ICs
General Description
The MAX3205E/MAX3207E/MAX3208E low-capacitance, 15kV ESD-protection diode arrays with an integrated transient voltage suppressor (TVS) clamp are suitable for high-speed and general-signal ESD protection. Low input capacitance makes these devices ideal for ESD protection of signals in HDTV, PC monitors (DVITM, HDMITM), PC peripherals (FireWire(R), USB 2.0), server interconnect (PCI ExpressTM, Infiniband (R) ), datacom, and interchassis interconnect. Each channel consists of a pair of diodes that steer ESD current pulses to VCC or GND. The MAX3205E/MAX3207E/MAX3208E protect against ESD pulses up to 15kV Human Body Model, 8kV Contact Discharge, and 15kV Air-Gap Discharge, as specified in IEC 61000-4-2. An integrated TVS ensures that the voltage rise seen on VCC during an ESD event is clamped to a known voltage. These devices have a 2pF input capacitance per channel, and a channel-tochannel capacitance variation of only 0.05pF, making them ideal for use on high-speed, single-ended, or differential signals. The MAX3207E is a two-channel device suitable for USB 1.1, USB 2.0 (480Mbps), and USB OTG applications. The MAX3208E is a four-channel device for Ethernet and FireWire applications. The MAX3205E is a six-channel device for cell phone connectors and SVGA video connections. The MAX3205E is available in 9-bump, tiny chip-scale (UCSPTM), and 16-pin, 3mm x 3mm, thin QFN packages. The MAX3207E is available in a small 6-pin SOT23 package. The MAX3208E is available in 10-pin MAX(R) and 16-pin, 3mm x 3mm TQFN packages. All devices are specified for the -40C to +125C automotive operating temperature range.
Features
Low Input Capacitance of 2pF Typical Low Channel-to-Channel Variation of 0.05pF from I/O to I/O High-Speed Differential or Single-Ended ESD Protection 15kV-Human Body Model 8kV-IEC 61000-4-2, Contact Discharge 15kV-IEC 61000-4-2, Air-Gap Discharge Integrated Transient Voltage Suppressor (TVS) Optimized Pinout for Minimized Stub Instances on Controlled-Impedance Differential-Transmission Line Routing -40C to +125C Automotive Operating Temperature Range UCSP Packaging Available
MAX3205E/MAX3207E/MAX3208E
Ordering Information
PART MAX3205EABL-T MAX3205EATE MAX3207EAUT-T MAX3208EAUB MAX3208EATE TEMP RANGE PINPACKAGE PKG CODE B9-2
-40C to +125C 9 UCSP-9
16 TQFN-EP* -40C to +125C T1633-4 (3mm x 3mm) -40C to +125C 6 SOT23-6 -40C to +125C 10 MAX -40C to +125C U6-1 U10-2
16 TQFN-EP* T1633-4 (3mm x 3mm)
*EP = Exposed pad. FireWire is a registered trademark of Apple Computer, Inc. PCI Express is a trademark of PCI-SIG Corporation. DVI is a trademark of Digital Display Working Group. HDMI is a trademark of HDMI Licensing, LCC. InfiniBand is a registered trademark of InfiniBand Trade Association. UCSP is a trademark and MAX is a registered trademark of Maxim Integrated Products, Inc.
Applications
DVI Input/Output Protection Set-Top Boxes PDAs/Cell Phones Graphics Controller Cards Displays/Projectors High-Speed, Full-Speed and Low-Speed USB Port Protection FireWire IEEE 1394 Ports Consumer Equipment High-Speed Differential Signal Protection
Typical Operating Circuit and Pin Configurations appear at end of data sheet.
Selector Guide
PART MAX3205EABL-T MAX3205EATE MAX3207EAUT-T MAX3208EAUB MAX3208EATE ESD-PROTECTED I/O PORTS 6 6 2 4 4 TOP MARK AES ACO ABVG -- ACN
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Dual, Quad, and Hex High-Speed Differential ESD-Protection ICs MAX3205E/MAX3207E/MAX3208E
ABSOLUTE MAXIMUM RATINGS
VCC to GND ...........................................................-0.3V to +6.0V I/O_ to GND ................................................-0.3V to (VCC + 0.3V) Continuous Power Dissipation (TA = +70C) 6-Pin SOT23 (derate 8.7mW/C above +70C)............696mW 9-Pin UCSP (derate 4.7mW/C above +70C) .............379mW 10-Pin MAX (derate 5.6mW/C above +70C) ...........444mW 16-Pin Thin QFN (derate 20.8mW/C above +70C) .1667mW Operating Temperature Range .........................-40C to +125C Storage Temperature Range .............................-65C to +150C Junction Temperature .....................................................+150C Lead Temperature (soldering, 10s) .................................+300C Bump Temperature (soldering) Infrared (15s) ...............................................................+220C Vapor Phase (60s) .......................................................+215C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +5V and TA = +25C.) (Note 1)
PARAMETER Supply Voltage Supply Current Diode Forward Voltage SYMBOL VCC ICC VF IF = 10mA TA = +25C, 15kV Human Body Model, IF = 10A Channel Clamp Voltage (Note 2) TA = +25C, 8kV Contact Discharge (IEC 61000-4-2), IF = 24A Positive transients Negative transients Positive transients Negative transients 0.65 CONDITIONS MIN 0.9 1 TYP MAX 5.5 100 0.95 VCC + 25 -25 VCC + 60 -60 VCC + 100 -100 -0.1 MAX3205EABL-T MAX3207EAUT Channel I/O Capacitance VCC = +3.3V, bias of VCC / 2 MAX3205EATE MAX3208EATE MAX3208EAUB Channel I/O to I/O Variation in Capacitance TRANSIENT SUPPRESSOR VCC Capacitance to GND ESD Trigger Voltage dV/dt 1V/ns (Note 3) 10 9 pF V CIN VCC = +3.3V, bias of VCC / 2, CI/O_ to GND 2.5 2.7 2.6 0.05 +0.1 3 3.2 3.1 pF pF A V UNITS V nA V
VC
TA = +25C, 15kV Air-Gap Positive transients Discharge (IEC 61000-4-2), Negative transients IF = 45A Channel Leakage Current
Note 1: Parameters are 100% production tested at +25C. Limits over temperature are guaranteed by design only. Note 2: Idealized clamp voltages. See the Applications Information section for more information. Note 3: Guaranteed by design, not production tested.
2
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Dual, Quad, and Hex High-Speed Differential ESD-Protection ICs
Typical Operating Characteristics
(VCC = +5V, TA = +25C, unless otherwise noted.)
CLAMP VOLTAGE vs. DC CURRENT
MAX3205E toc01
MAX3205E/MAX3207E/MAX3208E
LEAKAGE CURRENT vs. TEMPERATURE
MAX3205E toc02
INPUT CAPACITANCE vs. INPUT VOLTAGE
MAX3205E toc03
1.5 1.3 CLAMP VOLTAGE (V) 1.1 0.9 0.7 GND TO I/O_ 0.5 0.3 10 30 50 70 90 110 130 I/O_ TO VCC
10,000
4
INPUT CAPACITANCE (pF)
LEKAGE CURRENT (pA)
1000
3
100
2
10
1
1 150 -40 0 40 80 120 DC CURRENT (mA) TEMPERATURE (C)
0 0 1 2 3 4 5 INPUT VOLTAGE (V)
Pin Description
PIN MAX3205E TQFN 4, 5, 7, 12, 13, 15 1, 3, 6, 8, 9, 11, 14, 16 -- 2 10 EP UCSP A2, A3, B1, B3, C1, C2 -- MAX3207E SOT23 1, 4 MAX3208E MAX 1, 4, 6, 9 TQFN 4, 7, 12, 15 1, 3, 5, 6, 8, 9, 11, 13, 14, 16 -- 2 10 EP I/O_ ESD-Protected Channel NAME FUNCTION
3, 6
2, 5, 7, 10
N.C.
No Connection. Not internally connected. No Connection. The solder sphere is omitted from this location (see the Packaging Information section). Ground. Connect GND with a low-impedance connection to the ground plane. Power-Supply Input. Bypass VCC to GND with a 0.1F ceramic capacitor as close to the device as possible. Exposed Pad. Connect EP to GND.
B2 A1 C3 --
-- 2 5 --
-- 3 8 --
N.C. GND VCC EP
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Dual, Quad, and Hex High-Speed Differential ESD-Protection ICs MAX3205E/MAX3207E/MAX3208E
Detailed Description
The MAX3205E/MAX3207E/MAX3208E low-capacitance, 15kV ESD-protection diode arrays with an integrated transient voltage suppressor (TVS) clamp are suitable for high-speed and general-signal ESD protection. Low input capacitance makes these devices ideal for ESD protection of signals in HDTV, PC monitors (DVI, HDMI), PC peripherals (FireWire, USB 2.0), Server Interconnect (PCI Express, Infiniband), Datacom, and Inter-Chassis Interconnect. Each channel consists of a pair of diodes that steer ESD current pulses to V CC or GND. The MAX3205E, MAX3207E, and MAX3208E are two, four, and six channels (see the Functional Diagram). The MAX3205E/MAX3207E/MAX3208E are designed to work in conjunction with a device's intrinsic ESD protection. The MAX3205E/MAX3207E/MAX3208E limit the excursion of the ESD event to below 25V peak voltage when subjected to the Human Body Model waveform. When subjected to the IEC 61000-4-2 waveform, the peak voltage is limited to 60V when subjected to Contact Discharge. The peak voltage is limited to 100V when subjected to Air-Gap Discharge. The device protected by the MAX3205E/MAX3207E/ MAX3208E must be able to withstand these peak voltages, plus any additional voltage generated by the parasitic of the board. A TVS is integrated into the MAX3205E/MAX3207E/ MAX3208E to help clamp ESD to a known voltage. This helps reduce the effects of parasitic inductance on the VCC rail by clamping VCC to a known voltage during an ESD event. For the lowest possible clamp voltage during an ESD event, placing a 0.1F capacitor as close to VCC as possible is recommended.
Functional Diagram
MAX3207E
MAX3208E
MAX3205E
VCC
VCC
VCC
I/O1
I/O2
I/O1
I/O2
I/O3
I/O4
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
GND
GND
GND
4
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Dual, Quad, and Hex High-Speed Differential ESD-Protection ICs
Applications Information
Design Considerations
Maximum protection against ESD damage results from proper board layout (see the Layout Recommendations section). A good layout reduces the parasitic series inductance on the ground line, supply line, and protected signal lines. The MAX3205E/MAX3207E/MAX3208E ESD diodes clamp the voltage on the protected lines during an ESD event and shunt the current to GND or VCC. In an ideal circuit, the clamping voltage (VC) is defined as the forward voltage drop (VF) of the protection diode, plus any supply voltage present on the cathode. For positive ESD pulses: VC = VCC + VF For negative ESD pulses: VC = -VF The effect of the parasitic series inductance on the lines must also be considered (Figure 1). For positive ESD pulses:
d(IESD ) d(IESD ) VC = VCC + VF(D1) + L1 x + L2 x dt dt
During an ESD event, the current pulse rises from zero to peak value in nanoseconds (Figure 2). For example, in a 15kV IEC-61000 Air-Gap Discharge ESD event, the pulse current rises to approximately 45A in 1ns (di/dt = 45 x 109). An inductance of only 10nH adds an additional 450V to the clamp voltage, and represents approximately 0.5in of board trace. Regardless of the device's specified diode clamp voltage, a poor layout with parasitic inductance significantly increases the effective clamp voltage at the protected signal line. Minimize the effects of parasitic inductance by placing the MAX3205E/MAX3207E/MAX3208E as close to the connector (or ESD contact point) as possible. A low-ESR 0.1F capacitor is recommended between VCC and GND in order to get the maximum ESD protection possible. This bypass capacitor absorbs the charge transferred by a positive ESD event. Ideally, the supply rail (VCC) would absorb the charge caused by a positive ESD strike without changing its regulated value. All power supplies have an effective output impedance on their positive rails. If a power supply's effective output impedance is 1, then by using V = I x R, the clamping voltage of VC increases by the equation VC = IESD x ROUT. A +8kV IEC 61000-4-2 ESD event generates a current spike of 24A. The clamping voltage increases by VC = 24A x 1, or VC = 24V. Again, a poor layout without proper bypassing increases the clamping voltage. A ceramic chip capacitor mounted as close as possible to the MAX3205E/ MAX3207E/MAX3208E VCC pin is the best choice for this application. A bypass capacitor should also be placed as close to the protected device as possible.
MAX3205E/MAX3207E/MAX3208E
For negative ESD pulses:
d(IESD ) d(IESD ) VC = - VF(D2 ) + L1 x + L3 x dt dt
where, IESD is the ESD current pulse.
POSITIVE SUPPLY RAIL
L2
I 100% 90% IPEAK
D1 L1 I/O_ PROTECTED LINE D2
10% tR = 0.7ns to 1ns
L3 GROUND RAIL
30ns 60ns
t
Figure 1. Parasitic Series Inductance
Figure 2. IEC 61000-4-2 ESD Generator Current Waveform 5
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Dual, Quad, and Hex High-Speed Differential ESD-Protection ICs MAX3205E/MAX3207E/MAX3208E
15kV ESD Protection
ESD protection can be tested in various ways. The MAX3205E/MAX3207E/MAX3208E are characterized for protection to the following limits: * 15kV using the Human Body Model * 8kV using the Contact Discharge Method specified in IEC 61000-4-2 * 15kV using the IEC 61000-4-2 Air-Gap Discharge Method ESD Test Conditions ESD performance depends on a number of conditions. Contact Maxim for a reliability report that documents test setup, methodology, and results. and IEC 61000-4-2 is higher peak current in IEC 610004-2. Because series resistance is lower in the IEC 61000-4-2 ESD test model (Figure 5), the ESDwithstand voltage measured to this standard is generally lower than that measured using the Human Body Model. Figure 2 shows the current waveform for the 8kV, IEC 61000-4-2 Level 4, ESD Contact Discharge test. The Air-Gap Discharge test involves approaching the device with a charged probe. The Contact Discharge method connects the probe to the device before the probe is energized.
Human Body Model
Figure 3 shows the Human Body Model, and Figure 4 shows the current waveform it generates when discharged into a low impedance. This model consists of a 100pF capacitor charged to the ESD voltage of interest, which is then discharged into the device through a 1.5k resistor. IEC 61000-4-2 The IEC 61000-4-2 standard covers ESD testing and performance of finished equipment. The MAX3205E/ MAX3207E/MAX3208E help users design equipment that meets Level 4 of IEC 61000-4-2. The main difference between tests done using the Human Body Model
IP 100% 90% AMPERES 36.8% 10% 0 0 tRL TIME
Ir
PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE)
tDL CURRENT WAVEFORM
Figure 4. Human Body Model Current Waveform
RC 1M CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE
RD 1.5k DISCHARGE RESISTANCE DEVICE UNDER TEST HIGHVOLTAGE DC SOURCE
RC 50 to 100 CHARGE-CURRENTLIMIT RESISTOR
RD 330 DISCHARGE RESISTANCE DEVICE UNDER TEST
Cs 100pF
STORAGE CAPACITOR
Cs 150pF
STORAGE CAPACITOR
Figure 3. Human Body ESD Test Model
Figure 5. IEC 61000-4-2 ESD Test Model
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Dual, Quad, and Hex High-Speed Differential ESD-Protection ICs
Layout Recommendations
Proper circuit-board layout is critical to suppress ESDinduced line transients (See Figure 6). The MAX3205E/ MAX3207E/MAX3208E clamp to 100V; however, with improper layout, the voltage spike at the device can be much higher. A lead inductance of 10nH with a 45A current spike results in an additional 450V spike on the protected line. It is essential that the layout of the PC board follows these guidelines: 1) Minimize trace length between the connector or input terminal, I/O_, and the protected signal line. 2) Use separate planes for power and ground to reduce parasitic inductance and to reduce the impedance to the power rails for shunted ESD current. 3) Ensure short low-inductance ESD transient return paths to GND and VCC. 4) Minimize conductive power and ground loops. 5) Do not place critical signals near the edge of the PC board. 6) Bypass VCC to GND with a low-ESR ceramic capacitor as close to VCC as possible. 7) Bypass the supply of the protected device to GND with a low-ESR ceramic capacitor as close to the supply pin as possible.
MAX3205E/MAX3207E/MAX3208E
UCSP Applications Information
For the latest application details on UCSP construction, dimensions, tape carrier information, printed circuit board techniques, bump-pad layout, and recommended reflow temperature profile, as well as the latest information on reliability testing results, go to the Maxim website at www.maxim-ic.com/ucsp for the Application Note, UCSP--A Wafer-Level Chip-Scale Package.
Chip Information
DIODE COUNT: MAX3205E: 7 MAX3207E: 3 MAX3208E: 5 PROCESS: BiCMOS
Typical Operating Circuit
VCC L1 PROTECTED LINE VCC NEGATIVE ESDCURRENT PULSE PATH TO GROUND 0.1F L2 I/0 LINE I/0_ VCC PROTECTED CIRCUIT I/0
0.1F D1 I/O_ D2 VC
PROTECTED CIRCUIT
MAX3205E MAX3207E MAX3208E
GND
L3
Figure 6. Layout Considerations
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Dual, Quad, and Hex High-Speed Differential ESD-Protection ICs MAX3205E/MAX3207E/MAX3208E
Pin Configurations
TOP VIEW
N.C.
N.C. 14
I/O1
I/O6 GND A1 A2 A3 I/O5 N.C. I/O1 B1 1 2 3 4
16
15
13 I/O1 1 12 11 I/O3 N.C. VCC N.C. N.C. 3 4 I/O2 GND 2 6 N.C.
I/O2
MAX3205E
B3
I/O4
GND N.C. I/O6
MAX3207E
5
VCC
MAX3205E
10 9
I/O2
C1
C2 I/O3
C3
VCC 5 I/O5 6 N.C. 7 I/O4 8 N.C.
SOT23
UCSP (BUMPS ON BOTTOM)
THIN QFN
N.C. N.C. 14 N.C. 13 12 11 I/O2 N.C. VCC N.C. 10 9 5 N.C. 6 N.C. 7 I/O3 8 N.C. I/O1 15
16 I/O1 1 N.C. GND I/O2 N.C. 2 3 4 5 10 N.C. 9 I/O4 VCC N.C. I/O3 N.C. GND N.C. I/O4 1 2 3 4
MAX3208E
8 7 6
MAX3208E
MAX
THIN QFN
8
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Dual, Quad, and Hex High-Speed Differential ESD-Protection ICs
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
9LUCSP, 3x3.EPS
MAX3205E/MAX3207E/MAX3208E
PACKAGEOUTLINE,3x3UCSP 21-0093 I
1 1
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Dual, Quad, and Hex High-Speed Differential ESD-Protection ICs MAX3205E/MAX3207E/MAX3208E
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
10LUMAX.EPS
1 1
e
10
4XS
10
INCHES MAX DIM MIN 0.043 A 0.006 A1 0.002 A2 0.030 0.037 0.120 D1 0.116 0.118 D2 0.114 E1 0.116 0.120 0.118 E2 0.114 0.199 H 0.187 L 0.0157 0.0275 L1 0.037REF b 0.007 0.0106 e 0.0197BSC c 0.0035 0.0078 0.0196REF S 0 6
MILLIMETERS MAX MIN 1.10 0.05 0.15 0.75 0.95 2.95 3.05 2.89 3.00 2.95 3.05 2.89 3.00 4.75 5.05 0.40 0.70 0.940REF 0.177 0.270 0.500BSC 0.090 0.200 0.498REF 0 6
H
O0.500.1
0.60.1
1
1
0.60.1
TOPVIEW
BOTTOMVIEW
D2 GAGEPLANE A2 A b D1 A1
E2 c E1 L1
L
FRONTVIEW
SIDEVIEW
PROPRIETARYINFORMATION TITLE:
PACKAGEOUTLINE,10LuMAX/uSOP
APPROVAL DOCUMENTCONTROLNO. REV.
21-0061
I
10
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Dual, Quad, and Hex High-Speed Differential ESD-Protection ICs
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
6LSOT.EPS
MAX3205E/MAX3207E/MAX3208E
______________________________________________________________________________________
11
Dual, Quad, and Hex High-Speed Differential ESD-Protection ICs MAX3205E/MAX3207E/MAX3208E
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
D2 b
0.10M C A B
D D/2
D2/2
E/2
E2/2
C L
E
(NE-1)Xe
E2
L
C L
e
k (ND-1)Xe
C L
0.10 C 0.08 C A A2 A1 L
C L
L
e
e
PACKAGEOUTLINE 12,16L,THINQFN,3x3x0.8mm
21-0136
E
1
2
12
______________________________________________________________________________________
12x16L QFN THIN.EPS
Dual, Quad, and Hex High-Speed Differential ESD-Protection ICs
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX3205E/MAX3207E/MAX3208E
PKG REF. A b D E e L N ND NE A1 A2 k 0 MIN. 0.70 0.20 2.90 2.90 0.45
12L3x3 NOM. 0.75 0.25 3.00 3.00 0.50BSC. 0.55 12 3 3 0.02 0.05 0 0.25 0.20REF 0.25 0.65 0.30 MAX. 0.80 0.30 3.10 3.10 MIN. 0.70 0.20 2.90 2.90
16L3x3 NOM. 0.75 0.25 3.00 3.00 0.50BSC. 0.40 16 4 4 0.02 0.20REF 0.05 0.50 MAX. 0.80 0.30 3.10 3.10 PKG. CODES T1233-1 T1233-3 T1633-1 T1633-2 T1633F-3 T1633-4
EXPOSEDPADVARIATIONS
D2 MIN. 0.95 0.95 0.95 0.95 0.65 0.95 NOM. 1.10 1.10 1.10 1.10 0.80 1.10 MAX. 1.25 1.25 1.25 1.25 0.95 1.25 MIN. 0.95 0.95 0.95 0.95 0.65 0.95 E2 NOM. MAX. 1.10 1.10 1.10 1.10 0.80 1.10 1.25 1.25 1.25 1.25 0.95 1.25 PINID 0.35x45 0.35x45 0.35x45 0.35x45 JEDEC WEED-1 WEED-1 WEED-2 WEED-2
DOWN BONDS ALLOWED
NO YES NO YES N/A NO
0.225x45 WEED-2 0.35x45 WEED-2
NOTES: 1.DIMENSIONING&TOLERANCINGCONFORMTOASMEY14.5M-1994. 2.ALLDIMENSIONSAREINMILLIMETERS.ANGLESAREINDEGREES. 3.NISTHETOTALNUMBEROFTERMINALS. 4.THETERMINAL#1IDENTIFIERANDTERMINALNUMBERINGCONVENTIONSHALLCONFORMTO JESD95-1SPP-012.DETAILSOFTERMINAL#1IDENTIFIERAREOPTIONAL,BUTMUSTBELOCATED WITHINTHEZONEINDICATED.THETERMINAL#1IDENTIFIERMAYBEEITHERAMOLDOR MARKEDFEATURE. 5.DIMENSIONbAPPLIESTOMETALLIZEDTERMINALANDISMEASUREDBETWEEN0.20mmAND0.25mm FROMTERMINALTIP. 6.NDANDNEREFERTOTHENUMBEROFTERMINALSONEACHDANDESIDERESPECTIVELY. 7.DEPOPULATIONISPOSSIBLEINASYMMETRICALFASHION. 8.COPLANARITYAPPLIESTOTHEEXPOSEDHEATSINKSLUGASWELLASTHETERMINALS. 9.DRAWINGCONFORMSTOJEDECMO220REVISIONC.
PACKAGEOUTLINE 12,16L,THINQFN,3x3x0.8mm
21-0136
E
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.

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